Design for Test Digital - DfT 4.0
Companies must deliver good products to their customers; without defects and with minimal cost. Just reducing the cost of purchasing components, process and testing is no longer achieving the expected results
The challenge is how to detect or prevent the occurrence of defects, so that only good products are sent to the customer, at the lowest possible cost and at each cycle, generating learning and making fewer mistakes.
Traditional processes develop the prototype, then the process and then test what takes time or has the resource $, but even traditional DfT tools only work at the layout stage, which is too late in the process. This is killing some brands' profit or reputation.
Project data must be analyzed in the initial stage of the product's life cycle, importing schematic data or, in the worst case, in the 1st version of the layout, where changes will fit within the development flow.
Violations of electrical D f T rules must be identified and rectified prior to committing to the board layout to avoid costly re-designs of the project. These rules can include standard and customer-specific checks related to company requirements. With a centralized knowledge database, the same problems will never be repeated! And even better if all this is done automatically in a simple and effective way.
Test point requirements should also be identified in the pre-layout, during the schematic capture phase. This reduces the need for unnecessary test access, saving PCB space, especially on high-density boards.
TestWay simulates the test strategy, including any combination of testing and inspection machines, providing the highest test coverage. This unique combination provides electrical rule analysis, test point analysis, test strategy optimization, and test cost modeling based purely on schematic information. This, in turn, provides valuable layout guidelines that can be used to optimize the printed circuit board layout.
Once the PCBA layout is complete, a mechanical DfT analysis should be conducted to confirm that networks requiring test access are not compromised by solder mask, component contour, adjacent probe restrictions, etc. Depending on the experience of the team and the complexity of the board, the analysis can be done only once in the 1st layout version as shown in the diagram below:
