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Digital Test Coverage - Digital Twin

The flow vision of Design for Deliver Excellence, in the context of Industry 4.0 principles, applies to the introduction of new electronics driven by Excellent Test Coverage.


The goal of any test solution is to maximize test coverage, ensuring that the most defects are detected, while minimizing the cost of testing and the business as a whole.


If a product is not tested well enough, poor quality products will damage the reputation of the company and the brand. If a product is over-tested, it can negatively impact a variety of business processes, including production costs, process and delivery cycle times.


Do we know the defective electronics that cannot be shipped to our customer after testing?

REAL Production Model that few pay attention to


“TEST” – Test Coverage – TCR – is the percentage of defects that can be captured by a combination of electrical inspection and testing machines.

“FPY”- First Pass Yield is the percentage of boards that pass – PASS – the test that can no longer be considered a good measure of production quality. This is easily demonstrated by 0% test coverage, which will result in 100% first pass yield!
This leads to the extremely compelling question: IS A PLATE GOOD WHY IT PASSED THE TEST?


"FOR (For Repair)" - is the number of boards that failed the test and need to be repaired or scrapped - "scrapped".


Based on practical experience, the following question arises: "Are all defective products really defective?" OR "Are all the products that are shipped good?" The answer is clear to both questions: “NO!”.


“SLIP (Slip)” - is the leak rate, is a key metric and represents the defective products that will be shipped to the end customer. A potential disaster for your brand credibility or your business results.


Ultimately, “SLIP” is how end users will measure the quality they are receiving. If a PCBA is failing the product test, it is because the mounted board has dropped its exhaust (or slip) rate, this is usually much higher than expected.


There are two possible reasons for this situation to occur:

  • DPMO (Process Failures) numbers are higher than expected.

Test coverage (mostly unknown) combined is less than ideal.

Instigated? Curious? 

Digital and Revealed Test Coverage

When evaluating the results of a combination of testing techniques, the  TestWay  simulates a variety of testing strategies and predicts and reveals final and digital test coverage.


Initially, however, we must consider the metrics that can be used to calculate test coverage. This is the first mistake in the market, to complicate and each area or technique to have “its test coverage”.


It clearly doesn't work. Something is needed to assess test coverage that is reliable and can be easily updated to reflect increasing electronic complexity.


Consider all manufacturing defects within the defect universe, including: missing components, incorrect value, misalignment, incorrect polarity, damaged components, open circuits, short circuits, insufficient soldering and excessive soldering.


We must have testing techniques in place that are capable of detecting these defects. The ability to detect defects can be expressed by a coverage facet, so that each category of defect is aligned with coverage metrics.


The table in Figure 3 details the industry standard metrics that have been defined by Philips Research (MPS) and ASTER Technologies (PPVSF).


These metrics allow for the estimation of theoretical coverage, or measurement of actual coverage, for each inspection technique, or coverage of the combination of the various test techniques used or required.


No one testing technique can detect all defects. It is a combination of complementary testing techniques that provide excellent overall coverage. What we affectionately call green PPVS


When calculating test coverage, it is important to consider the DPMO that reflects the current manufacturing process.


In this way, test coverage can be aligned so that better coverage is provided where there is a greater opportunity for defects to occur during manufacturing.


In the test effectiveness formulas below, each defect category is associated with its corresponding coverage.



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